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ADE7953
ADE7953 INTERRUPTS
The ADE7953 interrupts are separated into two groups. The
first group of interrupts is associated with the voltage channel
and Current Channel A. The second group of interrupts is
associated with Current Channel B. See Table 22 and Table 24
for a list of the interrupts.
All interrupts are disabled by default with the exception of the
RESET interrupt that is located within the group of primary
interrupts. This interrupt is enabled by default and signals the
end of a software or hardware reset. On power-up, this interrupt
is triggered to signal that the ADE7953 is ready to receive
communication from the microcontroller. This interrupt should
be serviced as described in the Primary Interrupts (Voltage
Channel and Current Channel A) section prior to configuring
the ADE7953 .
PRIMARY INTERRUPTS (VOLTAGE CHANNEL AND
CURRENT CHANNEL A)
The primary interrupts are events that occur on the voltage
channel and Current Channel A. These interrupts are handled
by a group of three registers: the enable register, IRQENA
(Address 0x22C and Address 0x32C), the status register,
IRQSTATA (Address 0x22D and Address 0x32D), and the
reset status register, RSTIRQSTATA (Address 0x22E and
Address 0x32E). The bits in these registers are described in
Table 22 and Table 23.
When an interrupt event occurs, the corresponding bit in the
IRQSTATA register is set to 1. If the enable bit for this interrupt,
located in the IRQENA register, is set to 1, the external IRQ pin
is pulled to Logic 0. The status bits located in the IRQSTATA
register are set when an interrupt event occurs, regardless of
whether the external interrupt is enabled.
All interrupts are latched and require servicing to clear. To
service the interrupt and return the IRQ pin to Logic 1, the
status bits must be cleared using the RSTIRQSTATA register
(Address 0x22E and Address 0x32E). The RSTIRQSTATA
Data Sheet
register, but when the RSTIRQSTATA register is accessed, a read-
with-reset command is executed, clearing the status bits. After
completion of a read from this register, all status bits are cleared
to 0 and the IRQ pin returns to Logic 1.
CURRENT CHANNEL B INTERRUPTS
The Current Channel B interrupts are events that occur on
Current Channel B. Like the primary group of interrupts,
Current Channel B interrupts are handled by a group of three
registers: the enable register, IRQENB (Address 0x22F and
Address 0x32F), the status register, IRQSTATB (Address 0x230
and Address 0x330), and the reset status register, RSTIRQSTATB
(Address 0x231 and Address 0x331). The bits in these registers
are described in Table 24 and Table 25.
When an interrupt event occurs, the corresponding bit in
the IRQSTATB register is set to 1. The Current Channel B
interrupts do not have a dedicated output pin. This function
can be configured as an alternative output on Pin 1 (ZX),
Pin 21 (ZX_I), or Pin 20 (REVP) (see the Alternative Output
Functions section). If an output is enabled for interrupt events
on Current Channel B and the interrupt enable bit, located in
the IRQENB register, is set to 1, Pin 1, Pin 21, or Pin 20 is
pulled low if an interrupt event occurs on Current Channel B.
The status bits located in the IRQSTATB register are set when
an interrupt event occurs, regardless of whether an external
interrupt output is enabled.
All interrupts are latched and require servicing to clear. To
service the interrupt, the status bits must be cleared using the
RSTIRQSTATB register (Address 0x231 and Address 0x331).
The RSTIRQSTATB register contains the same interrupt status
bits as the IRQSTATB register, but when the RSTIRQSTATB
register is accessed, a read-with-reset command is executed,
clearing the status bits. After completion of a read from this
register, all status bits are cleared to 0 and the appropriate
output pin (if enabled) returns to Logic 1.
register contains the same interrupt status bits as the IRQSTATA
Rev. B | Page 50 of 72
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